1. Field of the Invention
This invention relates generally to the testing of Flash memory devices and, more particularly, to a test method of screening out Flash memory devices during wafer sort conducted at room temperature that would be hot temperature programming rejects discovered during class tests conducted at elevated temperature.
2. Discussion of the Prior Art
This application is related to application, Ser. No. 08/655,337 entitled "Method of Screening Hot Temperature Erase Rejects at Room Temperature" and application, Ser. No. 08/653,227 entitled "Method of Utilizing Redundancy Testing To Substitute for Main Array Programming and AC Speed Reads" both applications having a common assignee with this application and filed on the same date as this application.
The standard test method used for Flash memory devices includes testing at the wafer level and testing after each individual die has been packaged. The wafer level testing is commonly done at room temperature and is called wafer sort. The package level testing is done after the wafer has been sawed into single die and encapsulated in a package which is typically plastic. The package level testing is commonly called final test or class test and is done at an elevated temperature, usually from 70-130 degree Centigrade. Once the package level or class test is complete the Flash memory devices that pass the class test are marked and shipped to the customer.
The wafer sort is used to remove or screen-out the die that have a defect or defects which occur during the fabrication of the Flash wafer. The wafer sort is used to ensure that only those die that have a possibility of being shipped to a customer are encapsulated in a package. This is done to control the package cost since bad die are not packaged.
Presently, the class testing is still necessary since the wafer sort is done at room temperature and some die are sensitive to operations at elevated temperatures and there were no known tests that could be conducted during wafer sort which is conducted at room temperature that could screen programming rejects that would be discovered at elevated temperature testing. The operations that are most sensitive to elevated temperatures are speed sorting (a sort that determines the speed of the Flash memory device), programming, and certain low level leakage current testing. In addition, a part of class testing is to ensure that the encapsulation process did not damage the die.
A programming operation changes the logic state of a cell from a "1" (called "blank") to a logic "0" (called "programmed"). The programming and read operations are done at the byte level, that is, 8 cells (bits) at a time, on the Flash memory devices. The erase operation changes the logic of the cell to a "1" or blank state. The erase operation is done on all cells in the array at the same time. To prevent "over-erasure" of an individual cell, all cells must be programmed to a logic "0" before the erase operation. Over-erasure of a cell can cause problems during subsequent programming and read operations and in some cases would prevent the cell from being programmed. The Flash memory device must have all cells at a logic "1" when transferred to the class testing or when shipped to a customer. This means that if any cell is read as programmed, that is, read at a logic "0" then all cells must be programmed to a logic "0", read, erased, and reread to ensure all cells are blank, that is, are at a logic "1". Presently, this must be done at both wafer sort and class test.
One of the problems encountered is that the cells are not exactly the same, that is, some cells either program or erase faster or slower than others. It is necessary, therefore, to provide a series of programming pulses or erase pulses to a device. The key to a good device is that all cells in the device can be programmed or erased by being subjected to a series of program pulses or erase pulses with the number of pulses being within an acceptable range.
The wafer sort and class test require lengthy test sequences due to the large number of memory cells that need to be read, programmed, read again, erased, and read again. The number of cells in a Flash memory device is commonly on the order of 1-2 million cells. It is expected that this number will increase in the future.
What is needed is a test methodology that can be conducted at room temperature during wafer sort that can successfully screen out those Flash memory devices that would be rejected during elevated temperature programming testing during class test, thus negating the requirement to repeat the lengthy testing sequence during class test. The advantage of such a test methodology would be that (1) test time for each good Flash memory device would decrease leading to lower product cost, (2) class test yields would increase since elevated temperature programming rejects would not be packaged and subjected to class testing which would result (3) in lower overall packaging cost.